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4U et Fast Architecture SCSI Processor FAS368M he aS at Data Sheet D . w FAS368M package size, pin out, and transceivers differ Features
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QLogic Corporation
Compliance with ANSI X3T10/1142D SCSI Parallel Interconnect-2 (SPI-2) standard Compliance with ANSI SCSI configured automatically (SCAM) protocol levels 1 and 2 Sustained SCSI data transfer rates of up to: I 40 Mbytes/sec synchronous (Ultra and wide SCSI) I 14 Mbytes/sec asynchronous (wide SCSI) Synchronous DMA timing; DMA speed of 50 Mbytes/sec REQ and ACK programmable assertion and deassertion control Support for hot plugging Target and initiator block transfer sequences Bus idle timer Split-bus architecture Pipelined command structure On-chip, single-ended SCSI transceivers (48-mA drivers) On-chip, multimode, low voltage differential (LVD) drivers On-chip differential sense decoder Initiator and target roles Active negation 16-bit recommand counter Differential mode SCSI bus reset watchdog timer
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Product Description
The FAS368M is a new addition to the QLogic fast architecture SCSI processor (FAS) chip family. The FAS368M supports internal multimode LVD and single-ended (SE) transceivers, which allow the chip to support LVD and SE operations in initiator and target roles. The FAS368M is a single-chip controller for use in host and peripheral applications. To ensure firmware compatibility and provide FAS366U customers a seamless upgrade path, the FAS368M uses the same SCSI core, foundry, and process as the FAS366U. Note that the
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from the FAS366U. The FAS368M block diagram is shown in figure 1. The FAS368M implements QLogic's new SCSI target and initiator block transfer sequences. The block sequences reduce firmware overhead and are composed of the following new commands: Target Block Sequence (including the bus idle timer), Initiator Block Sequence, Load/Unload Block Registers sequences, Abort Block Sequence, and Disconnect Abort Block Sequence. The FAS368M supports both single-ended and differential mode SCSI operations and operates in initiator and target roles. The FAS368M has been optimized for interaction with a DMA controller and the controlling microprocessor. The versatile split-bus architecture supports various microprocessor and DMA bus configurations. A separate 8-bit microprocessor bus (PAD) provides access to all internal registers, and a 16-bit DMA bus (DB) provides a path for DMA transfers through the FIFO. Each bus is protected by a parity bit (byte-wide parity) to improve data integrity. During data transfer, the microprocessor has instant access to status and has the ability to execute commands.
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SCAM Implementation
The FAS368M supports levels 1 and 2 of the SCAM protocol. Refer to the latest revision of X3T10/855D, Annex B. The SCAM protocol requires direct access and control over the SCSI data bus and several of the SCSI phase and control signals. The majority of the SCAM protocol can be implemented in firmware at microprocessor speeds. The following SCAM features are supported in the hardware: s Arbitration without an ID s Slow response to selection with an unconfirmed ID s Detection of and response to SCAM selection
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QLogic Corporation
SCSI DATA BUS DB BUS 16 DATA PINS 2 PARITY PINS FIFO BLOCK REGISTERS COMMAND RECOMMAND COUNTER TRANSFER COUNT SEL/RESEL BUS ID SEL/RESEL TIMEOUT SEQUENCERS SYNC PERIOD SYNC OFFSET/ SYNC ASSERT/ SYNC DEASSERT CLOCK CONVERSION PAD BUS 8 DATA PINS 1 PARITY PIN CONFIGURATION SEQUENCE STEP 18 SCSI CONTROL PINS TRANSFER COUNTER 32 DATA PINS 4 PARITY PINS
INTERRUPT
STATUS
Figure 1. FAS368MBlock Diagram
Fast DMA Protocol
Fast DMA protocol is required for supporting the full bandwidth of Ultra, wide SCSI. The DREQ signal initiates DMA transfers and runs asynchronous to the user's clock. For read operations, DACK acts as a chip select to enable the FAS368M drivers onto the DMA bus. The chip select role of DACK helps support the burst timing of fast DMA mode. DACK selects the FAS368M after DREQ is asserted and is removed either after DREQ is deasserted or when the DMA transfer is paused. DBRD requests data from the FAS368M and DBWR validates data sent to the FAS368M. Data is valid around the rising (trailing) edge of DBRD or DBWR. DMA transfers are terminated by deasserting DREQ. Deassertion of DREQ is triggered by the leading edge of DBRD or DBWR (see timing parameter t1 in figures 2 and 3) under any of the following conditions: s To prevent FIFO overrun conditions s To prevent FIFO underrun conditions s When the required amount of data has been transferred
When DREQ is deasserted, the FAS368M ignores DBRD and DBWR. Data transfers do not take place unless DREQ is asserted. The FAS368M does not generate parity on the incoming DMA bus. Correct parity must always be supplied with the data. The DMA interface signals are listed in table 1. DMA timing is listed in table 2 and illustrated in figures 2 and 3. Table 1. DMA Interface Signals
Pin DREQ Type Active Level O High Description The FAS368M DMA request line begins and ends DMA cycles. The acknowledge is used as a chip select to activate FAS368M drivers and to acknowledge acceptance of DREQ. The trailing edge accepts data from the FAS368M for DMA read operations.
DACK
I
Low
DBRD
I
Rising edge
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FAS368M
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QLogic Corporation
Table 1. DMA Interface Signals (Continued)
Pin DBWR Type Active Level I Rising edge Description The trailing edge strobes data into the FAS368M FIFO on DMA write operations. This is the DMA data bus. Symbol tR7 tR8 tR9 tW1 Min. (ns) Max. (ns) 12 2 40 tR5 15 15 tR3 40 2 tW2 tW3 tW4 tW5 tW6 tW7
Table 2. DMA Timing (Continued)
Description DACK high to DB15-0 read offc DBRD low to DB15-0 read valid DBRD low to DB15-0 read DACK low to DBWR low DBWR assertion pulse width DBWR deassertion pulse width DBWR high to DACK high
d c
Min. (ns)
Max. (ns) 15 15
DB15-0
I/O
N/A
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0 tW5 15 15 tW3 40 10 5
Table 2. DMA Timing
Symbol t1 t2 t3 tR1 tR2 tR3 tR4 tR5 tR6 Description DBRD/DBWR low to DREQ lowa DACK high to DREQ high DACK high to DACK low DACK low to DBRD low DBRD assertion pulse width DBRD deassertion pulse width DBRD high to DACK highb onc
DBWR low to DBWR low cycle DB15-0 write setup to DBWR high DB15-0 write hold from DBWR high
DBRD low to DBRD low cycle DACK low to DB15-0 read
Table Notes aDREQ loading is 30 pf. bDBRD low to DACK high tR5 cData loading is 50 pf. dDBWR low to DACK high tW5
t2 DREQ t1 DACK t3
tR5 tR1 DBRD tR7 tR6 DB15-0 tR8 tR9 tR2 tR3 tR4
Figure 2. DMA Read Cycle
t2 DREQ t1 DACK tW5 tW1 DBRD tW2 tW3 tW4 t3
tW6 DB15-0
tW7
Figure 3. DMA Write Cycle
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QLogic Corporation
Interfaces
The FAS368M interfaces consist of the microprocessor bus and the SCSI bus. Pins that support these interfaces and other chip operations are shown in figure 4.
FAS368M
MICROPROCESSOR INTERFACE 4 A3-0 CS INT 8 PAD7-0 PADP PAUSE RD WR ACK/ACK ATN/ATN BSY/BSY CD/CD IO/IO MSG/MSG REQ/REQ RST/RST SD15-0/SD15-0 SDP1-0/SDP1-0 DMA AND MICROPROCESSOR INTERFACE DACK 16 2 DB15-0 DBP1-0 DBRD DBWR DREQ DIFFM DIFFSENS DIFFERENTIAL MODE SUPPORT SEL/SEL 4 2 2 32 2 2 2 2 2 2 2 SCSI INTERFACE
MODE1-0 RESETI RESET RESETO CLK VDD VSS
BUS CONFIGURATION
CLOCK
POWER AND GROUND
Figure 4. FAS368M Functional Signal Grouping
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QLogic Corporation
Packaging
The FAS368M is available in a 144-pin thin quad flat pack (TQFP). The mechanical drawings are illustrated in figure 3.
22.0 0.4 PIN 108 PIN 109 SEE DETAIL A PIN72 22.0 0.4 0.10 + 0.05 1.6 MAX 20.0 0.2 4 TYPICAL 20.0 0.2 PIN 73
0.1 0.1 INDEX MARK PIN 37 0.5 0.2 0.5 1.0 0.2 0.2 0.1
PIN 144 NOTE:
PIN 1
PIN 36 DETAIL A
ALL DIMENSIONS ARE IN MILLIMETERS. ALL DIMENSIONS ARE NOMINAL UNLESS SPECIFIED OTHERWISE.
Figure 3. FAS368M Mechanical Drawings
Electrical Characteristics
Table 4. Operating Conditions
Symbol VDD VDD IDDa IDDb TA Description Supply voltage (5 volt) Supply voltage (3 volt) Supply current (static IDD) Supply current (dynamic IDD) Ambient temperature 0 Minimum 4.75 3.3 V - 5% Maximum 5.25 3.3 V + 5% 1 TBD 70 Unit V V mA mA
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Table Notes Conditions that not within the operating conditions but within the absolute maximum stress ratings may cause the chip to malfunction. Capacitance in and out (CIN, COUT) is 15 pF maximum for all pins. aStatic IDD is measured with no clocks running and all inputs forced to VDD, all outputs unloaded, all bidirectional pins configured as inputs, and LVD mode disabled. bDynamic IDD is dependent on the application.
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QLogic Corporation
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FAS368M
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QLogic Corporation
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FAS368M
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QLogic Corporation
All other brand and product names are trademarks or registered trademark of their respective holders.
Specifications are subject to change without notice. QLogic is a trademark of QLogic Corporation.
(c)January 30, 1998 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200
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